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GL3523T
Overview

Genesys GL3523T is a 4-port, low-power, and configurable hub controller. It is compliant with the USB 3.1 specification. GL3523T integrates Genesys Logic self-developed USB 3.1 Gen 1 Super Speed transmitter/receiver physical layer (PHY) and USB 2.0 High-Speed PHY. It supports Super Speed, Hi-Speed, and Full-Speed USB connections and is fully backward compatible to all USB 2.0 and USB 1.1 hosts. GL3523T also implements multiple TT* (Note1) architecture providing dedicated TT* to each downstream (DS) port, which guarantees Full-Speed(FS) data passing bandwidth when multiple FS devices perform heavy loading operations. Furthermore, GL3523T has built-in 5V to 3.3V and 5V to 1.2V regulators, which saves customers’ BOM cost, and eases for PCB design.

 

GL3523T features the native fast-charging and complies with USB-IF battery charging specification rev1.2, it could fast-charge Apple, Samsung Galaxy devices, and any device complaint with BC1.2/1.1. It also allows portable devices to draw up to 1.5A from GL3523T charging downstream ports (CDP1) or dedicated charging port (DCP2). It can enable systems to fast charge handheld devices even during “Sleep” and “Power-off” modes.

All available packages for GL3523T are listed as the following tables.

 

Product Series

Package Type

Number of DFPs

Power Mgmt.

LED Support

GL3523T

QFN 76

4

Individual/ Gang

Green/Amber

 

*Note: TT (transaction translator) implements the control logic defined in Section 11.14 ~ 11.22 of USB specification revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub.

 

1 CDP, charging downstream port, the Battery Charging Rev.1.2-compliant USB port that does data communication and charges device up to 1.5A.

2 DCP, dedicated charging port, the Battery Charging Rev.1.2-compliant USB port that only charges devices up to 1.5A, similar to wall chargers.


  • Compliant with USB 3.1 Gen 1 Specification
  • Upstream port supports SuperSpeed (SS), HighSpeed (HS) and FullSpeed (FS) traffic
  • Downstream ports support SS, HS, FS, and LowSpeed (LS) traffic
  • 1 control pipe and 1 interrupt pipe
  • Backward compatible to USB specification Revision 2.0/1.1
  • Featuring fast-charging on all downstream ports and upstream port
  • Compliant with USB Battery Charging Revision v1.2, supporting CDP, DCP, and ACA-Dock
  • Downstream ports can be turned from a Standard Downstream Port (SDP) into Charging Downstream Port (CDP) or Dedicated Charging Port (DCP)
  • Downstream devices can be charged while upstream VBUS is not present, which can be applied on wall charger applications
  • Upstream port is capable of charging and data communicating simultaneously for portable devices supporting ACA-Dock or proprietary charging protocols
  • Supporting Apple 1A/2.1A/2.4A and Samsung Galaxy devices fast-charging
  • On-chip 8-bit micro-processor
  • RISC-like architecture
  • USB optimized instruction set
  • 1 cycle instruction execution (maximum)
  • Performance: 12 MIPS @ 12.5MHz (maximum)
  • With 256-byte RAM, 20K-byte internal ROM, and 24K-byte SRAM
  • Multiple Transaction Translator (TT) architecture
  • Providing dedicated TT control logics for each downstream port
  • Superior performance when multiple FS devices operate concurrently
  • Integrated USB transceiver
  • Improving output drivers with slew-rate control for EMI reduction
  • Internal power-fail detection for ESD recovery
  • Advanced power management and low power consumption
  • Supporting USB 3.1 U0/U1/U2/U3 power management states
  • Supporting USB Link Power Management (LPM) L0/L1/L2
  • Supporting individual/gang mode over-current detection for all downstream ports
  • Supporting both low/high-enabled power switches
  • Patented Smart Power Management
  • Configurable settings by firmware in SPI flash
  • Configurable charging port
  • Configurable 4/3/2 downstream ports, downstream port can be disabled/enabled by each specific port for USB3.1/USB2.0
  • Supporting full in-system programming firmware upgrade by SPI-flash and configuration by EEPROM
  • Supporting compound-device (non-removable setting on downstream ports)
  • Supporting customization VID/PID
  • Flexible design
  • Supporting Poly-fuse/Power-switch
  • Automatic switching between self-powered and bus-powered modes
  • Supporting electrical tuning for each specific port
  • Supporting programmable breathing LED
  • Supporting register setting by firmware
  • Supporting vendor command and SMBUS
  • Allow downstream ports to connect up to 8 devices, 4 x USB3.1 non-removable devices with 4 x USB2.0 non-removable devices or exposed ports
  • Low BOM cost
  • Single external 25 MHz crystal / Oscillator clock input
  • Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors
  • Built-in 5 to 3.3V and 5 to 1.2V regulator
  • Different package types available for various applications
  • Applications
  • Standalone USB hub/Docking station
  • Tablet/Ultrabook/NB
  • Motherboard
  • Monitor built-in hub, GPIOs can be programmed as I2C interface to easily update scalar firmware through USB interface
  • TV built-in hub
  • Compound device, such as hub-reader application
  • USB wall charger
  • Other consumer electronics
  • Customized applications
    • Dynamically disable/enable ports
    • GPIO signaling of ambient light sensor or rotation/position sensor

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