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Genesys Logic Announces Chandler Lin as the New President Date:2011/12/23

[ Taipei, Taiwan ]

    Genesys Logic, Inc (6104), the leading IC design company in mixed-signal high-speed I/O technologies, today announced Chandler Lin as its new president after a board meeting today. The appointment will be effective on Dec. 26. The current president, Y.C. Huang, will continue to serve as the company’s CEO. The board believes the new management team will strengthen the company's organization and energize its future business development.  
    Mr. Chandler Lin served as the president of System General Corporation's beforeits acquisition by Fairchild Semiconductor in January 2007. More recently, he was vice president at Advantech, the world No. 1 Industrial PC company. As aseasoned top executive, Chandler Lin has been well known and respected in the high-tech industry. Linwill be responsible for the company's operation efficiency and overall performance. He will directly lead several departments including productdevelopment, sales, operation, finance and marketing. Y.C. Huang will be in charge of strategic technology implementation,improvingdesign flow, and product qualityat design stage. In addition, Huang will work on engineering expertise cultivation,in order to elevate the company’s potential for innovation, and to develop the company’s future products. 

    The president, Chandler Lin, and CEO, Y.C. Huang, will lead Genesys Logic in tandem to tackle the challenges of an ever-changing and fast-paced technology industry, and to pursue innovation for the best benefits of its customers, shareholders and employees.

    Established in 1997, Genesys Logic's primary business is the design, research and development of electric circuits, semiconductors, digital communications products, computer peripherals and other related products. Genesys Logic has excellent R&D team, and its various diverse products are all based on its core technology, including high-speed USB 2.0、USB 3.0、PCI Express、SATA transfer interface and flash memory interface, allowing for the shared use of R&D resources.

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