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Genesys Logic Announces GigaCourier™/PHY at IDF 2003 Date:2003/09/17

[ Intel Developer Forum ]

Genesys Logic, Inc. (GLI), a leader in high-speed I/O communications, today announced GL230 (GigaCourier™/PHY), the first offering in its PCI Express™ product roadmap, at the Intel Developer Forum (IDF) in September 2003.


GL230 is the first PCI Express PIPE PHY in the industry implemented in a 0.18£gm standard digital CMOS process. GL230 fully complies with both the PCI Express™ Base Specification Revision 1.0a and the PHY Interface for the PCI Express™ (PIPE) Architecture version 1.0 from Intel. GL230 is a single lane transceiver, which can be expanded to 2/4/8/16/32 lanes in the future designs. It meets the demand of various bandwidth requirements for networking, graphics, storage, and many other applications.


GL230 supports Physical Coding Sub-Layer (PCS) and high speed serialization and de-serialization (SerDes.) The built-in PLL provides stable high-speed clocks for the robust operation of the SerDes at a serial interface speed of 2.5 Gbps as defined in PCI Express Base Spec Rev1.0a. In addition to the functionality defined in the PCI Express specification, GL230 provides several other features of its own. For example, the input parallel data bus could be either 8-bit or 16-bit wide, selectable by an external pin. Another example is the Polarity Inversion feature, which provides a flexible environment for the system designers. Peak-to-peak swing, de-emphasis level and pole-zero locations are a few other examples of the friendly programmable features of GL230. Low power consumption is another important feature of GL230. It leaves more room to the customers when planning power budget for their chips or systems.


GL230 also has Built-in Self Test (BIST) in place with various fixed and random patterns. The BIST provides several loop-back modes, enabling the functional self-checking of the analog transceiver.


Genesys Logic has a family of PCI Express™ products in the roadmap. The company is working on porting GL230 to a 0.13£gm process, which will be ready by Q4/2003. The PCI Express™ Transaction Layer and the Data Link Layer design for GL231 (GigaCourier™/TDM) will also be available by the end of 2003. In the first quarter of 2004, Genesys Logic will debut its PCI-X to PCI Express™ bridge controller - GL240 (GigaCoureir™/SFO. Porting to other major fundaries is also in the planning.


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